Logic Design And Verification Using Systemverilog -revised- Donald Thomas -

Bridging the gap between RTL design and rigorous verification for the working engineer and the advanced student. If you are a digital design engineer, a verification engineer moving closer to the design side, or a graduate student trying to survive the complexities of modern ASIC/FPGA flow, you know the struggle.

Additionally, the revised edition is still light on (Xilinx/Altera specific). This is a textbook for ASIC methodology, but 90% applies directly to high-end FPGAs. The Verdict: Buy it. Read it. Dog-ear it. If you are an early-career digital designer, Logic Design and Verification Using SystemVerilog (Revised) will cut your debug time in half. If you are a verification engineer, it will make you a better designer because you will finally understand why RTL engineers write "bad" code (and how to fix it). Bridging the gap between RTL design and rigorous

That camp is occupied almost entirely by Donald Thomas’ book, Logic Design and Verification Using SystemVerilog (Revised) . This is a textbook for ASIC methodology, but

Donald Thomas has written the book that sits between Digital Design 101 and UVM Reference Manual . It is the missing link. Dog-ear it