Clock Divider Verilog 50 | Mhz 1hz

module clock_divider_50M_to_1Hz ( input wire clk_50mhz, // 50 MHz input clock input wire rst_n, // Active-low reset output reg clk_1hz // 1 Hz output clock ); // 50 MHz → 1 Hz requires division by 50,000,000 // Count from 0 to 24,999,999 (toggle) then repeat // Total cycles: 50,000,000 = 2 × 25,000,000

reg [$clog2(MAX_COUNT+1)-1:0] counter;

// Instantiate the clock divider clock_divider_50M_to_1Hz uut ( .clk_50mhz(clk_50mhz), .rst_n(rst_n), .clk_1hz(clk_1hz) ); clock divider verilog 50 mhz 1hz

// Stage 1: 50 MHz → 100 Hz (divide by 500,000) clock_divider #(50_000_000, 100) stage1 (clk_50mhz, rst_n, clk_100hz); module clock_divider_50M_to_1Hz ( input wire clk_50mhz